1. Field of Invention
The present invention relates to a fuse circuit for final test trimming (FT-Trim) of an integrated circuit (IC) chip; particularly, it relates to such fuse circuit having an increased resistance to enhance an electrostatic discharge (ESD) protection, such that errors of FT-Trim of an IC chip are avoided.
2. Description of Related Art
Precise control of parameters of an IC chip in advanced electronic circuit systems has become a very important issue nowadays. In general, a considerable degree of errors of the parameters (including voltages, currents, etc.) may be generated by stress during packaging process. These errors may be ignored in the old days because the demand for precision of parameters is low. However, they are not ignorable now.
For improving the precision of the parameters of IC chips, FT-Trim is a common industry practice. This approach is to read the parameters after the IC is packaged, and to calculate differences between the readings and the design settings. The number of bits to be trimmed is calculated according to the differences, and specific fuses are broken to compensate the differences, such that the readings can be more closer to the design settings. Basically, the IC chip will not be processed after the FT-Trim, so there is no more impact on the parameters after FT-Trim.
FIG. 1 shows a schematic diagram of a conventional fuse circuit 10 for FT-Trim of the IC chip. As shown in FIG. 1, a fuse circuit 10 includes an electrical fuse 11 which is connected with a control switch Q1 in series between a power pin and a grounding pin GND. The control switch Q1 receives a control signal to determine whether the control switch Q1 turns ON, whereby a conductive path is formed between the power pin and the grounding pin GND, and current flows through the electrical fuse 11 for a predetermined time to break it and open the fuse circuit 10.
An ESD protection device is normally provided in the circuitry, which is also coupled between the power pin and the grounding pin GND, so the fuse circuit 10 and the ESD device are usually connected in parallel. The ESD device is for protecting the circuitry from ESD damages. However, ESD tests include exerting high voltages from the power pin and from the grounding pin respectively, and the ESD protection device may not protect the fuse circuit 10 during the ESD test from the grounding pin. More specifically, FIGS. 2A and 2B show two prior art circuits respectively, wherein FIG. 2A shows that the fuse circuit 10 is connected in parallel with an ESD protection device 15, and FIG. 2B shows that a fuse circuit 20 is connected in parallel with an ESD device 25. The fuse circuit 10 includes the control switch Q1 and the fuse circuit 20 includes a control switch Q2, wherein the control switch Q1 is an N-type metal oxide semiconductor (MOS) device, and the control switch Q2 is a P-type MOS device. When the power pins receive a positive voltage, it will be discharged from the power pins through the ESD protection devices 15 and 25 to the grounding pins GND, and the electrical fuses 11 and 21 will not be broken in this condition. However, when the grounding pins GND receive a positive voltage, it may be discharged from the grounding pins GND through parasitic diodes D1 and D2 of the control switches Q1 and Q2 to the power pins, and the electrical fuses 11 and 21 may be broken; thus, the parameters of the IC chip may shift and cause errors.
In view of the above, to overcome the drawbacks in the prior art, the present invention proposes a fuse circuit for FT-Trim of an IC chip, which provides a higher resistance to enhance the ESD protection, such that an incorrect trimming of FT-Trim of the IC chip is avoided.